The present invention relates generally to a method of erasing a flash memory cell, and more particularly, to a method of erasing a flash memory cell having a stacked gate structure at an increased rate while minimizing the loss of stored data.
Referring to FIG. 1, a flash memory cell generally includes a gate in which a tunnel oxide film 2, a floating gate 3, a dielectric film 4 and a control gate 5 are stacked on a channel of a semiconductor substrate 1. A source 6 and a drain 7 are formed in the semiconductor substrate 1 on either side of the gate.
The flash memory cell is typically programmed or erased by applying a bias voltage condition to the semiconductor substrate 1, the control gate 5, the source 6 and the drain 7. To program the flash memory cell, hot electrons are injected into the floating gate 3. On the other hand, to erase the flash memory cell, electrons injected into the floating gate 3 are discharged via the semiconductor substrate 1.
Erasing a flash EEPROM device typically involves changing all of the flash memory cells constituting a chip to the same state. In other words, the threshold voltages of all of the flash memory cells are changed to the same state.
The threshold voltage of a flash memory cell generally depends on the amount of charges injected into the floating gate 3. Therefore, in order to change the threshold voltages of all of the flash memory cells into the same state, electrons injected into the floating gate 3 are simultaneously discharged, a process which is usually performed using the prior art Fowler-Nordheim (F-N) tunneling method. As explained below, the use of the prior art F-N tunneling method overcomes a number of problems.
First, as electrons injected into a floating gate 3 typically have very low kinetic energy, they are unable to jump over a potential barrier of about 3.1 eV in the tunnel oxide film 2.
Second, although the electrons injected into the floating gate 3 of the flash memory cell are simultaneously discharged during the erasure operation, power consumption is minimized as the current flow is limited to the discharge of the electrons from the floating gate 3.
In the case of a flash EEPROM device having a sub-quarter design rule, that is, 0.25 xcexcm, an erasure operation is performed using the prior art channel F-N tunneling method, as shown in FIG. 2.
FIG. 2 shows a flash memory cell having a triple well structure. Using a prior art method to erase the flash memory cell, a negative bias voltage (xe2x88x92V) is applied to a control gate 5, a positive bias voltage (+V) is applied to a P-well 1a and to a N-well 1b of a semiconductor substrate 1, while the source 6 and the drain 7 are floated. This results in the electrons ("THgr"), previously injected into the floating gate 3, being discharged via the semiconductor substrate 1. Using the prior art channel F-N tunneling effect causes the tunneling region to become wider than when using a prior art junction erasure effect. As the dopant concentration of the channel becomes uniform, the number of flash memory cells that are erased early as a result of the induced electromagnetic field is reduced, so that the distribution of the threshold voltages after the implementation of the prior art erasure operation becomes constant. More specifically, as the dopant concentration of the channel and the well is increased, the number of holes that accumulate on the surface of the semiconductor substrate and the distribution of the electromagnetic field become uniform. As a result, the distribution degree becomes more constant. Also, as the speed is increased, the number of flash memory cells that are slowly erased is reduced. Therefore, the source 6 and the drain 7, that is, the junction region, is floated.
Referring to FIG. 3, using the prior art F-N tunneling effect, typically requires that a high electromagnetic field of more than 10 MV/cm be formed at both sides of the tunnel oxide film 2. Therefore, a high negative potential must be applied to the floating gate 3. In addition, the thickness of the dielectric film 4 must be reduced in order to increase the coupling capacitance (Cfg) between the control gate 5 and the floating gate 3, to which a negative bias voltage (xe2x88x92V) is applied.
The electromagnetic field (E) may be determined using Equation 1, where V is the applied voltage and t is the thickness of a dielectric film. Therefore, the thickness of the tunneling oxide film 2, acting as a dielectric film between the floating gate 3 and the channel, must be reduced.
E=V/t xe2x80x83xe2x80x83Equation 1 
However, if the thickness of the dielectric film existing on and below the floating gate 3 is reduced, a number of problems may occur.
The flash EEPROM device is a nonvolatile memory device which stores data by injecting hot electrons into the floating gate 3. The stored data is often required to be stored for a period of ten or more years. An electromagnetic field is typically formed toward the direction of the floating gate 3 if hot electrons are over-charged into the floating gate 3. If the thickness of the dielectric film is too thin, electrons flow out of the floating gate as shown in FIG. 4. As a result, stored data may be transformed or lost.
Typically, if the thickness of the dielectric film is reduced, the speed of the erasure operation is increased but the conservation characteristic of the stored data is degraded. Therefore, there is a need for a new method of increasing the speed of the erasure operation while maintaining the thickness of the dielectric film.
In accordance with an aspect of the invention, a method is provided for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain and (e) a well, where the gate includes: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. The method includes the steps of floating the source and the drain, applying a negative bias voltage to the control gate, applying a positive bias voltage to the well to thereby create a positive bias voltage in the source and the drain, applying a ground voltage to the well at a first time while maintaining the negative bias voltage a the control gate and subsequently applying a ground voltage to the control gate.
In accordance with an alternative aspect of the invention, a method is provided for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain and (e) a well, where the gate includes: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. The method includes the steps of applying a negative bias voltage to the control gate, applying a positive bias voltage to the well, creating a positive bias voltage in the source and the drain, applying a ground voltage to the control gate and simultaneously floating the well, the source and the drain.
In accordance with another aspect of the invention, a method is provided for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a P-well formed in the semiconductor substrate and (f) a N-well formed in the semiconductor substrate, where the gate includes: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. The method includes the steps of floating the N-well, the source and the drain, applying a negative bias voltage to the control gate, applying a positive bias voltage to the P-well, applying a ground voltage to the P-well, applying a ground voltage to the control gate, creating a ground voltage at the source and the drain and applying a ground voltage to the N-well.
In accordance with yet another aspect of the invention, a method is provided for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, where the gate includes: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. The method includes the steps of floating the source and the drain, applying a positive bias voltage to the control gate, applying a negative bias voltage to the well to thereby create a negative bias voltage in the source and the drain, applying a ground voltage to the well at a first time while maintaining the positive bias voltage at the control gate and subsequently applying a ground voltage to the control gate.